library verilog;
use verilog.vl_types.all;
entity MultUnSignPipe is
    generic(
        pmi_dataa_width : integer := 8;
        pmi_datab_width : integer := 8;
        pmi_pl          : integer := 1;
        module_type     : string  := "Mult"
    );
    port(
        PUA             : in     vl_logic_vector;
        PUB             : in     vl_logic_vector;
        PUClock         : in     vl_logic;
        PUClkEn         : in     vl_logic;
        PUAclr          : in     vl_logic;
        puproduct       : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_dataa_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_datab_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_pl : constant is 1;
    attribute mti_svvh_generic_type of module_type : constant is 1;
end MultUnSignPipe;
